The present invention generally relates to a common-memory controlling method and apparatus, and more particularly to a common-memory controlling method and apparatus in which a plurality of central processing units are connected to a common-memory, waiting time being reduced when the common-memory is simultaneously accessed by the plurality of central processing units.
A common-memory controlling apparatus is disclosed in Japanese Laid-Open Patent Application No. 3-2052. In this common-memory controlling apparatus, each of central processing units (CPUs) connected to a common-memory is provided with an arbitration code setting circuit, an arbitration code cyclic circuit and a bus arbitration circuit which are interconnected through a bus. A priority level of each of the CPUs is cycled by altering an arbitration code for each arbitration cycle. Accordingly, equal opportunity of a priority for using the bus can be provided to each of the CPUs.
However, since a plurality of CPUs are connected to the common-memory through the bus, there is a problem in that if a CPU having a long access time is connected, a waiting time for other CPUs is increased.